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ADE7854/ADE7858/ADE7868/ADE7878
POWER-UP PROCEDURE
3.3V – 10%
2.0V ± 10%
ADE78xx
Data Sheet
PSM0 READY
0V
~26ms
~40ms
MICROPROCESSOR
MAKES THE
MICROPROCESSOR
SETS PM1 PIN TO 0;
APPLY VDD TO CHIP
POR TIMER
TURNED ON
ADE78xx
FULLY
POWERED UP
RSTDONE CHOICE BETWEEN
INTERRUPT I 2 C AND SPI
TRIGGERED
Figure 26. Power-Up Procedure
The ADE7854 / ADE7858 / ADE7868 / ADE7878 contain an on-
chip power supply monitor that supervises the power supply
(VDD). At power-up, the device is inactive until VDD reaches
2 V ± 10%. When VDD crosses this threshold, the power supply
monitor keeps the device in the inactive state for an additional
26 ms to allow VDD to rise to 3.3 V ? 10%, the minimum
recommended supply voltage.
The PM0 and PM1 pins have internal pull-up resistors, but it is
necessary to set the PM1 pin to Logic 0 either through a
microcontroller or by grounding the PM1 pin externally, before
powering up the chip. The PM0 pin can remain open as it is
held high, due to the internal pull-up resistor. This ensures that
PSM0 (normal) mode. The time taken from the chip being
powered up completely to the state where all functionality is
enabled, is about 40 ms (see Figure 26). It is necessary to ensure
that the RESET pin is held high during the entire power-up
procedure.
If PSM0 mode is the only desired power mode, the PM1 pin can
serial port. To use the SPI port, toggle the SS/HSA pin three times
from high to low.
To lock I 2 C as the active serial port, set Bit 1 (I2C_LOCK) of the
CONFIG2 register to 1. From this moment, the device ignores
spurious toggling of the SS/HSA pin, and a switch to the SPI
Immediately after entering PSM0 mode, all registers in the
values, including the CONFIG2 and LPOILVL registers.
The ADE7854 / ADE7858 / ADE7868 / ADE7878 signal the end of
the transition period by pulling the IRQ1 interrupt pin low and
setting Bit 15 (RSTDONE) in the STATUS1 register to 1. This
bit is cleared to 0 during the transition period and is set to 1
when the transition ends. Writing the STATUS1 register with
the RSTDONE bit set to 1 clears the status bit and returns the
IRQ1 pin high. Because RSTDONE is an unmaskable interrupt,
Bit 15 (RSTDONE) in the STATUS1 register must be cancelled
for the IRQ1 pin to return high. Wait until the IRQ1 pin goes low
before accessing the STATUS1 register to test the state of the
RSTDONE bit. At this point, as a good programming practice,
cancel all other status flags in the STATUS1 and STATUS0 registers
by writing the corresponding bits with 1.
Initially, the DSP is in idle mode and, therefore, does not
execute any instructions. This is the moment to initialize all
See the Digital Signal Processor section for the proper procedure
to initialize all registers and start the metering.
If the supply voltage, VDD, falls lower than 2 V ± 10%, the
state, which means that no measurements or computations
are executed.
port is no longer possible.
If SPI is the active serial port, any write to the CONFIG2 register
locks the port, and a switch to the I 2 C port is no longer possible.
must be powered down or the device must be reset by setting
the RESET pin low. After the serial port is locked, the serial port
selection is maintained when the device changes from one
PSMx power mode to another.
Rev. H | Page 26 of 100
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